Field of the Invention
The present invention relates to a semiconductor apparatus, and particularly to a semiconductor apparatus employing copper as a wiring material.
Description of the Related Art
In recent years, improved fine semiconductor processes employ copper wiring. Copper wiring has a problem in that it is difficult to directly etch the copper using a mask formed of resist. Accordingly, the copper wiring is formed as follows. That is to say, grooves (openings) are formed in an insulating layer, and a copper wiring film is formed on the entire area of a substrate using a sputtering method or a CVD method. Subsequently, the surface of the wiring film is ground down to the upper face of the wiring film.
Such a copper wiring process has a problem of so-called “dishing”, which is a phenomenon in which the copper wiring has irregularities in thickness due to position irregularities in grinding rate in the grinding process in which the wiring layer is ground over a wide area. In order to prevent dishing from occurring, the upper limit of the wiring width is defined by a process rule.
[Patent Document 1]
Japanese Patent Application Laid Open No. H11-150114
In semiconductor circuits, in order to distribute a power supply line or a ground line to multiple portions, wiring having a certain level of width (which will be referred to as “distribution wiring” in this specification) is formed in vicinity of pads for wire bonding (bonding pads). Also, a line through which an analog or digital signal having a large amplitude is transmitted (which will be referred to as “power line” in this specification) needs to be formed with a certain level of line width. There is a need to form such a distribution wiring and a power line with low impedance. However, the dishing restricts the form of the wiring, leading to a problem in that it is difficult to reduce the impedance of such wiring.